1. Field of the Invention
This invention relates to a display driver such as, for example, a liquid crystal display (LCD) driver.
2. Description of the Related Art
Various display drivers are known, and a system construction of an exemplary one of conventional LCD drivers is shown in block diagram in FIG. 4.
LCD drivers are generally divided into two types including a driver which employs an IAPT (Improved Alt and Pleshko Technique) which is used popularly and an LCD driver which employs an IHAT (Improved Hybrid Addressing Technique) disclosed, for example, in Proceeding of the SID, Vol. 24/3, p.259 or in Collection of Drafts for the 1988 International Display Research Conference, IEEE, p.80.
Referring to FIG. 4, where the LCD driver shown is of the type which is based on the IAPT, a row driver 2 outputs a selection for each one line, and data corresponding to the selected line is outputted from a column driver 3. Where the IAPT is employed, the column driver and the row driver are both required to have a high voltage withstanding property, for example, against approximately 20 V.
On the other hand, where the LCD driver shown in FIG. 4 is of the type which is based on the IHAT, the row driver 2 outputs a selection signal for each plurality of lines, for example, for each two lines. This allows the column driver to have a voltage withstanding property against, for example, approximately 5 V (the row driver is required to have a voltage withstanding property against approximately 35 V). Where the IHAT is employed, since the column driver can be realized with a process of a 5 V system, a control circuit, a display RAM (random access memory) and some other circuits, which are normally provided externally of such column driver where the IAPT is employed, can be built in the column driver. In the circuit of FIG. 4, a control circuit in the column driver 3 (master chip) controls a column driver 4 (slave chip) and the row driver 2 with control signals. Meanwhile, display data from a CPU (not shown) are directly stored into display RAMs in the column drivers 3 and 4.
The LCD driver shown in FIG. 4 requires a large number of voltages as illustrated in FIG. 5. Referring to FIG. 5, for the column drivers 3 and 4, a logic ground potential GND and a logic power supply voltage V.sub.CC2 are used for a logic system for a CPU interface (I/F). Meanwhile, for an LCD driving system, an LCD driving voltage V.sub.0, another LCD driving voltage V.sub.1, a further LCD driving voltage V.sub.2 and an LCD driving power supply voltage V.sub.CC1 are required. Here, the logic ground potential GND and the LCD driving power supply voltage V.sub.CC1 are used also as outputs of control signals to the row driver 2. Meanwhile, for the row driver 2, the logic ground potential GND and the LCD driving power supply voltage V.sub.CC1 are used for a logic system for an interface of a control signal from the column driver 3. On the other hand, an LCD driving voltage V.sub.SS, the LCD driving voltage V.sub.1 and an LCD driving voltage V.sub.DD are required for the LCD driving system.
Subsequently, a driving method for the LCD is described. The row driver 2 outputs the LCD driving voltage V.sub.1 for non-selection, but outputs LCD driving voltage V.sub.DD or LCD driving voltage V.sub.SS for selection. Whether the voltage V.sub.DD should be outputted or the voltage V.sub.SS should be outputted for selection is based on a predetermined pattern. This pattern is incorporated in the control circuit in the column driver and is transmitted to the row driver using a control signal.
Meanwhile, each of the column drivers performs calculation based on the display data and the output pattern of the row driver, and selects and outputs one of the voltages V.sub.0, V.sub.1 and V.sub.2 in accordance with a result of the calculation. An output switch section is included in the column driver and performs such selection of an output voltage. An equivalent circuit of an example of the output switch section is shown in FIG. 6. Referring to FIG. 6, the output switch section includes a decoder circuit 6 for decoding a signal from a logic circuit in the column driver, and analog switches 7A, 7B and 7C which are opened or closed in response to output signals of the decoder circuit 6. In order to realize the circuit shown in FIG. 6 with an integrated circuit, each of the analog switches 7A, 7B and 7C is formed from such a p-channel MOS transistor (pMOS transistor) Q.sub.P1 and an n-channel MOS transistor (nMOS transistor) Q.sub.N1 connected in parallel as shown in FIG. 7. The back gate electrode (an electrode communicated with a region of a MOS transistor in which a channel is formed such as, for example, a silicon crystal substrate or a well formed in such substrate) of the pMOS transistor Q.sub.P1 is connected to the LCD driving power supply voltage V.sub.CC1. Meanwhile, the back gate electrode of the nMOS transistor Q.sub.N1 is connected to the logic ground potential GND. A signal C from the decoder circuit is inputted in non-reversed and reversed states to the gate electrodes of the two MOS transistors Q.sub.P1 and Q.sub.N1. Accordingly, the two MOS transistors Q.sub.P1 and Q.sub.N1 exhibit a same conduction state such that they both exhibit an on state or an off state in response to the signal C to connect or disconnect an input point IN (to which the voltage V.sub.0, V.sub.1 or V.sub.2 is supplied) and an output point OUT to or from each other.
In the conventional LCD driver described above, the logic ground potential GND for the column driver and the LCD driving voltage V.sub.0 for the column driver must have the relationship of GND.ltoreq.V.sub.0 without fail. This is described below.
It is first assumed that, of the output switch section of the column driver shown in FIG. 6, the analog switch 7C is at the potential V.sub.0 lower than the logic ground potential GND. In this instance, the potential V.sub.0 at the input point IN of the analog switch shown in FIG. 7 is lower than then the logic ground potential GND. In particular, in the nMOS transistor Q.sub.N1 in FIG. 7, the potential at an n+ region (a source region or a drain region) (which connects to the input point IN) exhibits a lower potential than a p region (channel region) which is at the ground potential GND. As a result, there is the possibility that a pn junction between the channel region and the input point IN may be biased in a forward direction and current may flow in a direction from the ground toward the input point IN, resulting in incomplete operation, deterioration in performance or destruction of the IC. If, as a countermeasure against this, the ground potential GND of the column driver is set to a negative potential together with the LCD driving voltage V.sub.0, then this results in incoincidence in level at the CPU interface I/F and makes transfer of display data impossible. Consequently, the potential V.sub.0 must be kept higher than the logic ground potential GND without fail.
Further, in order to adjust the contrast of the LCD, the potential differences of the potentials V.sub.0, V.sub.2, V.sub.DD and V.sub.SS from the voltage V.sub.1 are varied. Here, if the potential V.sub.0 is set variable, then there is the possibility that, depending upon the adjustment of the contrast, the potential V.sub.0 may become lower than the ground potential GND. Accordingly, an LCD driving power supply circuit 1 is required to keep the potential V.sub.0 to the ground potential GND as seen in FIG. 8. On the other hand, for the level power supply to the LCD, a tolerance of .+-.several mV is required. Therefore, if the potential V.sub.0 is fixed to the ground potential GND, then a high degree of accuracy is required for the absolute value of each of the potentials V.sub.1, V.sub.2, V.sub.DD and V.sub.EE with respect to the logic ground potential GND. However, it is usually difficult to require the tolerance of .+-.several mV for a DC/DC converter. Consequently, outputs of a DC-DC converter 8 cannot be used directly as the potentials V.sub.DD and V.sub.SS, and buffer amplifiers 9A and 9B, a reference circuit 10 for adjusting the potentials V.sub.DD and V.sub.SS and so forth are required. As a result, there is a problem in that not only the number of parts of the power supply circuit increases but also the current consumption of the power supply circuit increases.